The present invention relates to CAM (Content Addressable Memory).
Heretofore, complete parallel CAMs (Content Addressable Memories), which are also called associative memories, have been widely known as semiconductor storage circuits having the functions of performing the identity detection of retrieval data and stored data concurrently in terms of all bits and outputting the storage address of identity data or data (see "Design of Super LSI," pp 176-177, edited by Tetsuya Iizuka and supervised by Takuo Sugano, Baifukan).
However, the bitwise configuration of a typical conventional CAM memory comprising SRAM cells and exclusive NOR circuits has made it impossible to provide CAM having a large-sized cell and consequently a capacity at a level fit for practical use.
In many IC cards that have recently been commercialized as personal data bases, for instance, no CAM has been arranged as stated above. In such an IC card, an arrangement has been made to find out data for the intended purpose by sequentially retrieving data one after another from ROM (Read Only Memory) in which the data are prestored. For this reason, the greater the number of data becomes, as in language dictionary such as Japanese and English-Japanese dictionaries, the more it requires time to retrieve data. In other words, what has high- speed, flexible retrieval functions is still nonexistent.
If all data are made retrievable at a time as in the case of CAM, not by retrieving data one by one with the aid of software from the conventional ROM and the like used to store the data in the prior art, data retrieval from the IC card equipped with a large capacity ROM may be implemented with flexibility at high speed.
U.S. Pat. No. 3,701,980 (October 1972) and Japanese Patent Laid-Open No. 194196/1989, for instance, suggest the possibility of large capacity associative memories. The former U.S patent discloses a CAM memory cell construction with DRAM as a base, having a set of ordinary 2-bit memories, whereas the latter discloses CAM with an EPROM nonvolatile memory as a base, also having a set of ordinary 2-bit EPROM memories. Consequently, both of them can be subjected to integration larger in scale than that of CAM with SRAM as a base.
Notwithstanding, the construction with DRAM as a base still poses a problem in view of its area size. In the case of CAM with EPROM as a base, flexible write/read is impossible.
As set forth above, there has not yet been proposed a means effective in giving birth to a large scale integrated flexible CAM.